1. Field of the Invention
The present invention relates to a data processing device including a first signal processing processor which is called a priority processor and which operates according to operating cycles, a second signal processing processor and a common circuit having at least a memory function and being connected to the first and second processor by means of a switching circuit, which switching circuit being controlled by a switching signal produced by a control unit, which switching signal produces, when it is at a first level, a connection to the first processor and when it is at a second level a connection to the second processor, which first processor being connected to the control unit and provided for generating a preparation signal and applying it to the control unit.
2. Prior Art
Such devices are well known. On this subject one can consult in particular the European Patent Application 0,021,287 which corresponds to U.S. Pat. No. 4,422,142. In this document, there is a description of a device in which the common circuit is a memory capable of being addressed by two data processing systems. These systems are constituted in the usual way on the basis of microprocessors. The device described in the abovementioned patent application enables the avoidance of conflicts due to a simultaneous request from the two microprocessors relating to this common memory.
The known device is not very suited to the case in which the priority system must truly have priority over the other system in the use of this memory and this during the next operating cycle. This occurs when one of the systems includes a signal processing microprocessor operating according to fast cycles and when it is necessary to delay its operation as little as possible. The other system, having management functions can gain access to this common circuit with a less sustained frequency.